Switching power supply circuits employing switching converters such for example as flyback converters and forward converters are widely known. These switching converters form a rectangular waveform in switching operation, and therefore there is a limit to suppression of switching noise. It is also known that because of their operating characteristics, there is a limit to improvement of power conversion efficiency.
Accordingly, various switching power supply circuits using a resonant converter have been proposed (see for example Japanese Patent Laid-Open No. Hei 11-332233), and put to practical use. A resonant converter can readily provide high power conversion efficiency, and achieve low noise because the resonant converter forms a sinusoidal waveform in switching operation. The resonant converter has another advantage of being able to be formed by a relatively small number of parts.
FIG. 24 is a circuit diagram showing an example of a conventional switching power supply circuit having a resonant converter. In the power supply circuit shown in the figure, a partial voltage resonant circuit is combined with a current resonant converter of an externally excited type.
In the power supply circuit shown in this figure, a full-wave rectifying and smoothing circuit comprising a bridge rectifier circuit Di and one smoothing capacitor Ci is provided to a commercial alternating-current power supply AC. As a result of a full-wave rectifying operation by the bridge rectifier circuit Di and the smoothing capacitor Ci, a rectified and smoothed voltage Ei (direct-current input voltage) is obtained across the smoothing capacitor Ci. This rectified and smoothed voltage Ei has a level equal to that of an alternating input voltage VAC.
The current resonant converter supplied with the direct-current input voltage and switching the direct-current input voltage has two MOS-FET switching devices Q1 and Q2 connected to each other by half-bridge coupling as shown in the figure. Damper diodes DD1 and DD2 formed by body diodes are connected in a direction shown in the figure in parallel with the switching devices Q1 and Q2 between a drain and a source of the switching devices Q1 and Q2, respectively.
A partial resonant capacitor Cp is connected in parallel with the switching device Q2 between the drain and the source of the switching device Q2. A capacitance of the partial resonant capacitor Cp and a leakage inductance L1 of a primary winding N1 form a parallel resonant circuit (a partial voltage resonant circuit). Then, a partial voltage resonant operation, in which voltage resonance occurs only when the switching devices Q1 and Q2 are turned off, is obtained.
The power supply circuit is provided with an oscillation and drive circuit 2 formed by a general-purpose IC, for example, for switching-driving the switching devices Q1 and Q2. The oscillation and drive circuit 2 has an oscillating circuit and a driving circuit. The oscillating circuit and the driving circuit apply a drive signal (a gate voltage) of a required frequency to gates of the switching devices Q1 and Q2. Thereby the switching devices Q1 and Q2 perform switching operation so as to be turned on/off alternately at the required switching frequency.
An isolated converter transformer PIT is provided to transmit a switching output of the switching devices Q1&nbsp; and Q2 to a secondary side. One end of the primary winding N1 of the isolated converter transformer PIT is connected via a series connection of a primary side parallel resonant capacitor C1 to a junction (a switching output point) between the source of the switching device Q1 and the drain of the switching device Q2, whereby the switching output is transmitted.
Another end of the primary winding N1 is connected to a primary side ground.
A capacitance of the series resonant capacitor C1 and the leakage inductance L1 of the isolated converter transformer PIT including the primary winding N1 form a primary side series resonant circuit for converting an operation of a primary side switching converter into a current resonance type operation.
According to the above description, the primary side switching converter shown in this figure obtains the current resonance type operation by the primary side series resonant circuit (L1-C1) and the partial voltage resonant operation by the partial voltage resonant circuit (Cp//L1) described above.
That is, the power supply circuit shown in this figure employs a form in which a resonant circuit for making the primary side switching converter a resonant converter is combined with another resonant circuit. In the present specification, such a switching converter will be referred to as a complex resonant converter.
Though not described with reference to a figure, the isolated converter transformer PIT has an E-E-shaped core formed by combining E-shaped cores made of a ferrite material with each other. The isolated converter transformer PIT has a primary side winding part and a secondary side winding part divided from each other. The primary winding N1 and a secondary winding (N2A and N2B) to be described next are wound around the central magnetic leg of the E-E-shaped core.
Two secondary windings N2A and N2B divided by being provided with a center tap are wound as the secondary winding of the isolated converter transformer PIT. An alternating voltage corresponding to the switching output transmitted to the primary winding N1 is induced in the secondary windings N2A and N2B.
In this case, the center tap of the secondary windings N2A and N2B is connected to a secondary side ground. A full-wave rectifier circuit comprising rectifier diodes D01 and D02 and a smoothing capacitor C0 is connected to the secondary windings N2A and N2B as shown in the figure. Thereby a secondary side direct-current output voltage EO is obtained as a voltage across the smoothing capacitor C0. The secondary side direct-current output voltage EO is supplied to a load side not shown in the figure, and also inputted from a branch point as a detection voltage for a control circuit 1 to be described next.
The control circuit 1 supplies a detection output corresponding to change in level of the secondary side direct-current output voltage EO to the oscillation and drive circuit 2. The oscillation and drive circuit 2 drives the switching devices Q1 and Q2 so as to vary switching frequency according to the supplied detection output of the control circuit 1. Thus varying the switching frequency of the switching devices Q1 and Q2 stabilizes the level of the secondary side direct-current output voltage.
Operating waveforms when the power supply circuit having the circuit configuration shown in this figure meets a load condition of low voltage and high current are shown in FIG. 25. The operating waveforms shown in FIG. 25 were obtained when a measurement was performed under a condition of the alternating input voltage VAC=100 V and load power Po=125 W. The condition of the low voltage and the high current in this case is a condition of the secondary side direct-current output voltage Eo=5 V and a primary side series resonance current Io as a switching current of the primary side switching converter=25 A.
In obtaining the experimental result of the operating waveforms shown in FIG. 25, conditions and parts and elements and the like of the power supply circuit are selected as follows.
First, numbers of turns of the secondary windings N2A and N2B and the primary winding N1 are set such that a voltage level induced per T (turn) of the secondary side winding is 5 V/T. Specifically, the secondary winding N2A=N2B=1 T and the primary winding N1=30 T.
Then, a gap about 1.0 mm is formed in the central magnetic leg of the E-E-shaped core of the isolated converter transformer PIT. Thereby a coupling coefficient of about 0.85 is obtained between the primary winding N1 and the secondary windings N2A and N2B.
The primary side series resonant capacitor C1=0.068 g F and the partial voltage resonant capacitor Cp=330 pF are selected. As the rectifier diodes Do1 and Do2, 50A/40V Schottky diodes are selected.
A voltage V1 across the switching device Q2 in the waveform chart of FIG. 25 corresponds to an on/off state of the switching device Q2. Specifically, the voltage V1 is a rectangular wave, having a zero level during a period T2 when the switching device Q2 is turned on and being clamped at a predetermined level during a period T1 when the switching device Q2 is turned off. A switching current IDS2 flowing through the switching device Q2//the damper diode DD2 has a waveform such that during the period T2, the switching current IDS2 flows through the damper diode DD2 and is thus of a negative polarity at a time of turn-on, and is then inverted to flow through the drain and the source of the switching device Q2 with a positive polarity, and such that the switching current IDS2 is at a zero level during the off period T1.
The switching device Q1 performs switching so as to be turned on/off alternately with the switching device Q2. Therefore a switching current IDS1 flowing through the switching device Q1//the damper diode DD1 has a waveform shifted 180° in phase with respect to the switching current IDS2.
A primary side series resonance current Io flowing through the primary side series resonant circuit (C1-L1) connected between the switching output point of the switching devices Q1 and Q2 and the primary side ground is a waveform resulting from a synthesis of a sinusoidal wave component as the resonance current of the primary side series resonant circuit (C1-L1) and a sawtooth wave component produced by an exciting inductance of the primary winding N1, the waveform corresponding to a synthetic waveform of the switching current IDS1 and the switching current IDS2.
A measurement condition of the load power Po=125 W in this case is a condition of a heavy load close to a maximum as a load condition met by the power supply circuit shown in FIG. 24. In the condition of the heavy load in a range of load power handled by the power supply circuit, a rectified current on the secondary side is in a discontinuous mode.
Specifically, as shown in FIG. 25, a secondary winding voltage V2 occurring at the secondary winding N2A has a waveform clamped at a predetermined absolute value level only during a period when the primary side series resonance current Io flows in the form of a sinusoidal wave, and has a zero level during an interval when the sawtooth wave component produced by the exciting inductance flows as the primary side series resonance current Io between the periods when the primary side series resonance current Io flows in the form of a sinusoidal wave. A waveform obtained by inverting the secondary winding voltage V2 occurs at the secondary winding N2B.
Thus, a rectified current 11 flowing through the rectifier diode Do1 and a rectified current 12 flowing through the rectifier diode Do2 flow only in periods DON1 and DON2, respectively, during which the primary side series resonance current Io flows in the form of a sinusoidal wave. Neither of the rectified currents I1 and I2 flows in other periods. That is, the secondary side rectified current flows into the smoothing capacitor discontinuously.
A forward-direction voltage drop of the rectifier diodes Do1 and Do2 formed by Schottky diodes is 0.6 V. In the above-described operation on the secondary side, since the rectified currents I1 and I2 have a fairly high level of 35 Ap as shown in the figure, a conduction loss by these rectifier diode devices is noticeable, and thus a power loss is increased. As a result of an actual measurement, DC-to-DC power conversion efficiency when the direct-current input voltage (rectified and smoothed voltage Ei)=130 V is only about 86%.
As techniques for reducing the conduction loss of the rectified current on the secondary side, a synchronous rectifier circuit is known which performs rectification by MOS-FETs having a low on resistance. FIG. 26 shows an example of configuration of such a synchronous rectifier circuit using a winding voltage detection system.
Incidentally, FIG. 26 shows only a configuration on a secondary side of an isolated converter transformer PIT. A configuration on a primary side is the same as in FIG. 24. As a constant-voltage control system, a switching frequency control system is employed which variably controls switching frequency of a primary side switching converter according to level of a secondary side direct-current output voltage Eo.
A power supply circuit employing the secondary side configuration shown in FIG. 26 also meets the same condition of low voltage and high current (VAC=100 V, load power Po=125 W, Eo=5 V, and Io=25 A) as in the case of FIG. 24.
Also in this case, one end of each of secondary windings N2A and N2B having the same number of turns as a secondary winding is connected to a center tap. However, an output of the center tap is connected to a positive electrode terminal of a smoothing capacitor C0. Another end of the secondary winding N2A is connected to a secondary side ground (a negative electrode terminal side of the smoothing capacitor C0) via a drain and a source of an N-channel MOS-FET Q3. Similarly, another end of the secondary winding N2B is connected to the secondary side ground (the negative electrode terminal side of the smoothing capacitor C0) via a drain and a source of an N-channel MOS-FET Q4. That is, in this case, the MOS-FETs Q3 and Q4 are inserted in series in respective rectified current paths of the secondary windings N2A and N2B on the negative electrode side. Body diodes DD3 and DD4 are connected to the drain and the source of the MOS-FETs Q3 and Q4, respectively.
A driving circuit for driving the MOS-FET Q3 is formed by connecting a gate resistance Rg1 between a junction between the secondary winding N2B and the drain of the MOS-FET Q4 and a gate of the MOS-FET Q3, and connecting a resistance R11 between the gate of the MOS-FET Q3 and the secondary side ground.
Similarly, a driving circuit for driving the MOS-FET Q4 is formed by connecting a gate resistance Rg2 between a junction between the secondary winding N2A and the drain of the MOS-FET Q3 and a gate of the MOS-FET Q4, and connecting a resistance R12 between the gate of the MOS-FET Q4 and the secondary side ground.
When an on voltage is applied to a gate of a MOS-FET, a region between a drain and a source of the MOS-FET becomes equivalent to a mere resistor, so that a current flows bidirectionally. When the MOS-FET is to be made to function as a secondary side rectifying device, the current needs to flow in only a direction to charge the positive electrode terminal of the smoothing capacitor C0. If a current flows in an opposite direction, a discharge current flows from the smoothing capacitor C0 to the isolated converter transformer PIT side, so that power cannot be efficiently transmitted to a load side. Also, the opposite current causes heat generation of the MOS-FET, noise and the like, and invites a switching loss on the primary side.
The driving circuits described above are circuits for switching-driving the MOS-FETs Q3 and Q4 so that current flows in only the direction to charge the positive electrode terminal of the smoothing capacitor C0 (that is, from the drain to the source) on the basis of detection of a voltage of the secondary winding.
A waveform chart of FIG. 27 shows operation of the power supply circuit employing the secondary side configuration shown in FIG. 26 (the primary side configuration is the same as in FIG. 24) when the load power Po=125 W. As described above, the load power Po=125 W in this case is a condition of substantially a maximum load.
In this figure, a voltage V1 across a switching device Q2 and a corresponding secondary winding voltage V2 obtained across the secondary windings N2A and N2B are in timing similar to that in FIG. 24. Incidentally, the secondary winding voltage V2 shown in FIG. 27 has a polarity as viewed from a junction between the secondary winding N2A and the gate resistance Rg2. The secondary winding voltage V2 is of an opposite polarity as viewed from a junction between the secondary winding N2B and the gate resistance Rg1.
At the time of arrival of a period during which the secondary winding voltage V2 of the polarity shown in this figure is clamped at a predetermined level of negative polarity, the driving circuit for driving the MOS-FET Q4 operates to apply an on voltage at a level set by the gate resistance Rg2 and the resistance R12 to the gate of the MOS-FET Q4.
Similarly, at the time of arrival of a period during which the secondary winding voltage (V2) of the polarity opposite to that shown in this figure is clamped at a predetermined level of negative polarity, the driving circuit (the gate resistance Rg1 and the resistance R11) for driving the MOS-FET Q3 operates to apply an on voltage to the gate of the MOS-FET Q3.
Thus, rectified currents I1 and I2 of positive polarity flow through the MOS-FETs Q3 and Q4 in periods DON1 and DON2, respectively, as shown in the figure. The rectified currents I1 and I2 are 35 Ap as in the case of the circuit of FIG. 24 (the rectified currents I1 and I2 in the waveform chart of FIG. 25). However, the MOS-FETs Q3 and Q4 have a low on resistance, and thus a conduction loss of the rectified currents can be greatly reduced as compared with the rectifier diodes Do1 and Do2 formed by Schottky diodes. In addition, as is understood from the fact that the driving circuits are formed by only resistive elements, the winding voltage detection system has an advantage in that the driving circuit system is of a simple configuration.
However, in the condition of a heavy load corresponding to FIG. 27 (the load power Po=125 W), the secondary side rectified current in this power supply circuit is also in a discontinuous mode. This is indicated by discontinuity between the periods DON1 and DON2 in FIG. 27.
In the discontinuous mode, even when a current for charging the smoothing capacitor Co as the rectified currents I1 and I2 becomes a zero level, a current flows through the primary winding N1 of the isolated converter transformer PIT in the same direction. This indicates that in the foregoing waveform chart of FIG. 25, the sawtooth wave current component produced by the exciting inductance of the primary winding N1 flows as the primary side series resonance current Io in periods other than the periods DON1 and DON2 with the same polarity as in immediately preceding timing. Therefore, in actuality, the polarity of a voltage induced in the secondary windings N2A and N2B is not inverted, and in the meanwhile the MOS-FETs Q3 and Q4 maintain an on state without being completely turned off. Thus, a current in an opposite direction flows as the rectified currents I1 and I2 in the periods other than the periods DON1 and DON2 as shown in the figure. The rectified currents I1 and I2 in the opposite direction in the periods other than the periods DON1 and DON2 cause ineffective power. Since the rectified currents I1 and I2 in these periods have a relatively high level of 8 Ap, an amount of ineffective power is correspondingly large.
Thus, when the synchronous rectifier circuit employs the winding voltage detection system, while the conduction loss of the rectified currents is reduced, it is difficult to effectively improve total power conversion efficiency because of occurrence of ineffective power as described above.
A waveform chart of FIG. 28 shows operation of the power supply circuit employing the secondary side configuration shown in FIG. 26 under a condition of a light load.
As with the configuration of the power supply circuit shown in FIG. 24 as described above, the power supply circuit shown in FIG. 26 in practice performs constant-voltage control by controlling switching frequency. When the secondary side direct-current output voltage is increased under a condition of a light load, the power supply circuit operates to increase the switching frequency to decrease the secondary side direct-current output voltage, whereby the secondary side direct-current output voltage is stabilized.
In such a light-load condition, the secondary side winding voltage V2 is inverted in substantially the same timing as the voltage V1 across the switching device Q2 as shown in FIG. 28. Accordingly, the secondary side rectified currents I1 and I2 flow so as to continuously charge the smoothing capacitor Co without a period of discontinuity between periods DON1 and DON2. That is, a continuous mode is obtained. In this case, there are no periods when the rectified currents I1 and I2 in the opposite direction flow as in the operation at the heavy load as shown in FIG. 27, and thus correspondingly no ineffective power is produced.
Thus, the power supply circuit having the configuration obtained by replacing the secondary side rectifier circuit system with the synchronous rectifier circuit using the winding voltage detection system still has the problem of decrease in power conversion efficiency at the time of heavy load.
As techniques for solving the problem of occurrence of ineffective power caused by the rectified currents in the opposite direction as shown in FIG. 27, a synchronous rectifier circuit using a rectified current detection system is known. The rectified current detection system is a technique that turns off a MOS-FET before a rectified current for charging a smoothing capacitor Co becomes a zero level.
FIG. 29 shows an example of configuration of a synchronous rectifier circuit using this rectified current detection system. Incidentally, for simplicity of description, this figure shows a configuration for half-wave rectification.
In the rectified current detection system, a current transformer TR is provided to detect a current flowing through a secondary winding N2. A primary winding Na of the current transformer is connected to an end part of the secondary winding N2 and a drain of a MOS-FET Q4. A source of the MOS-FET Q4 is connected to a negative electrode terminal of a smoothing capacitor Co.
A secondary winding Nb of the current transformer is connected in parallel with a resistance Ra, and also connected in parallel with diodes Da and Db such that directions of forward voltages of the diodes Da and Db are opposite to each other, whereby a parallel connection circuit is formed. Further, the parallel connection circuit is connected with a comparator 20. A reference voltage Vref is inputted to an inverting input of the comparator 20. A junction between the reference voltage Vref and the inverting input of the comparator 20 is connected to an end part of a side where an anode of the diode Da and a cathode of the diode Db are connected in the parallel connection circuit. A non-inverting input of the comparator 20 is connected with an end part of a side where a cathode of the diode Da and an anode of the diode Db are connected in the parallel connection circuit.
In this case, an output of the comparator 20 is amplified by a buffer 21 and then applied to a gate of the MOS-FET Q4.
FIG. 30 shows operation of the circuit having the configuration shown in FIG. 29.
When a voltage induced in the secondary winding N2 becomes higher than a voltage (Eo) across the smoothing capacitor Co, a rectified current Id first starts to flow in a direction from an anode to a cathode of a body diode of the MOS-FET Q4 so as to charge the smoothing capacitor Co. Since the rectified current Id flows through the primary winding Na of the current transformer, a voltage Vnb corresponding to the rectified current Id flowing through the primary winding Na is induced in the secondary winding Nb of the current transformer. The comparator 20 compares the voltage Vnb with the reference voltage Vref. When the voltage Vnb exceeds the reference voltage Vref, the comparator 20 outputs an H level. This H level output is applied as an on voltage from the buffer 21 to the gate of the MOS-FET Q4 to turn on the MOS-FET Q4. Thus the rectified current Id flows from the drain to the source of the MOS-FET Q4. FIG. 30 shows the rectified current Id flowing with positive polarity.
Then, as the level of the rectified current Id is lowered with passage of time and correspondingly the voltage Vnb becomes lower than the reference voltage Vref, the comparator 20 inverts the output. The inverted output is output via the buffer 21 to discharge a gate capacitance of the MOS-FET Q4 and thereby turn off the MOS-FET Q4. Incidentally, the remaining rectified current Id at this point in time flows via a body diode DD4 within a short time.
With such an operation, the MOS-FET Q4 is turned off before the rectified current Id becomes a zero level. Thus, the flowing of the currents in the opposite direction through the MOS-FETs during the periods of discontinuity of the rectified currents as shown in FIG. 27 does not occur, so that ineffective power is not produced and power conversion efficiency is correspondingly increased.
For example, a measurement result obtained shows that DC-to-DC power conversion efficiency when the configuration on the secondary side of the power supply circuit shown in FIG. 24 is a synchronous rectifier circuit using the rectified current detection system for full-wave rectification which circuit is based on the configuration shown in FIG. 29 is improved to about 90% under the same condition as that of FIG. 25, FIG. 27 and the like.
As is understood from FIG. 29, however, the synchronous rectifier circuit of the above-described rectified current detection system requires, for one MOS-FET, at least one current transformer set and a relatively complex driving circuit system for driving the MOS-FET by an output of the current transformer. This complicates the circuit configuration, leading to disadvantages of decrease in manufacturing efficiency, increase in cost, increase in size of a circuit board, and the like.
In particular, when the synchronous rectifier circuit of the rectified current detection system is provided on the secondary side with the configuration of the primary side switching converter shown in FIG. 24 as a basis, a double-wave rectifier circuit needs to be formed on the secondary side. Therefore two current transformers and two driving circuit systems as described above are required for the MOS-FETs Q3 and Q4, thus aggravating the above problem.
Thus, the winding voltage detection system and the rectified current detection system are in a tradeoff relation in that the winding voltage detection system is disadvantageous in terms of power conversion efficiency because of ineffective power but enables a simple circuit configuration, whereas the rectified current detection system is advantageous in terms of power conversion efficiency because ineffective power is not produced but makes circuit configuration complex.